In recent years, significantly high data transfer rate is required for data transfer between semiconductor devices (between CPUs and memories for example). To accomplish high data transfer rate, the amplitude of input/output signals is increasingly reduced. If the input/output signals have reduced amplitudes, the desired accuracy of impedances of output buffers becomes severe.
The impedance of the output buffer varies depending on process conditions during the manufacturing. Also, during its actual use, the impedance of the output buffer is affected by variations in ambient temperature and power source voltage. When high impedance accuracy is required for the output buffer, output buffers that can adjust their impedance are utilized (Japanese Patent Application Laid-open Nos. 2002-152032, 2004-32070, 2006-203405, and 2005-159702). The impedance of such an output buffer is adjusted by circuits generally called “calibration circuit(s)”.
As disclosed in Japanese Patent Application Laid-open Nos. 2006-203405, and 2005-159702, the calibration circuit includes a replica buffer with the same configuration as the output buffer. When a calibration operation is performed, with an external resistor connected to a calibration terminal, the voltage of the calibration terminal is compared to the reference voltage and the impedance of the replica buffer is adjusted accordingly. The result of adjustment of the replica buffer is then reflected in the output buffer, and the impedance of the output buffer is thus set to the desired value.
In the sequence of calibration operations, an adjustment step that includes comparison of voltage and update of impedance of each of replica buffers is performed for a plurality of times. The impedance of the replica buffer is thus made to be close to the desired value.
However, the comparison of voltage and the change of impedance of the replica buffer in the calibration operation take a certain amount of time. Therefore, if the frequency of an external clock is high, the adjustment step cannot be performed every time the external clock is activated. In such a case, an internal clock with lower frequency is generated by dividing the external clock and the adjustment step is performed in synchronization with the internal clock.
The period in which the calibration operation is performed (a calibration period) is usually determined by the number of external clock cycles (e.g., 64 clock cycles). As the number of divisions of the external clock is increased, the number of adjustment steps performed during the calibration period is reduced. That is, assuming that the number of external clock cycles that determines the calibration period is indicated by m and the number of divisions is indicated by n, the number of activations of the internal clock in a calibration period, i.e., the number of adjustment steps is indicated by m/n. If the frequency of the external clock is increased, the number of divisions n must be increased, and thus the number of adjustment steps performed in a calibration period is further reduced.
In addition, in the calibration operation, the replica buffer that has the same circuit configuration as a pull-up circuit included in the output buffer is adjusted, and then the replica buffer that has the same circuit configuration as a pull-down circuit included in the output buffer is adjusted. Consequently, in conventional calibration circuits, a calibration period is divided into the first half and the second half. During the first half, the pull-up replica buffer is adjusted and the pull-down replica buffer is adjusted during the second half.
Accordingly, the numbers of adjustment steps performed for the pull-up and pull-down replica buffers are reduced by half, respectively, and thus a sufficient calibration operation is not performed.
Further, since the ordinary calibration circuit performs a first adjustment step by using the final code in the previous calibration operation, the impedance is not updated in the first adjustment step. The impedance update begins at a second adjustment step. Consequently, the number of impedance updates is less than the number of adjustment steps by one. Therefore, as the number of divisions is increased, the number of actual impedance updates is drastically reduced.
For example, assuming that the number of external clock cycles that determines the calibration period m is 64 clock cycles and the number of divisions n is 8, the number of activations of the internal clock in a calibration period is eight (=64/8). This number is assigned to the pull-up side and the pull-down side on halves. The number of adjustment steps is four both on the pull-up side and on the pull-down side. Because the impedance is not updated in the first adjustment step, the number of impedance updates is three (=4−1) both on the pull-up side and on the pull-down side.
If the speed of the external clock is increased and the number of divisions n is 16, the number of activations of the internal clock is only four (=64/16). The number of adjustment steps is two both on the pull-up side and on the pull-down side. The number of impedance updates is one (=2−1) If the speed of the external clock is more increased and the number of divisions n is also more increased, the number of impedance updates is zero. In such a case, the calibration operation cannot be performed.